A chronology of Ainekko (nekko.ai) and its open-source community AI Foundry, written Wed 16 Sep 2026 (week 38) by Yaroslav Bulatov for Thomas Ahle (Normal Computing, author of spicenn2) and Mitchell Nahmias (Sphere Semi, ex-Luminous Computing). Built from public primary sources (SEC filings, press releases, the OpenHW/AI Foundry repositories, Dave Ditzel's retrospective slides, EE Times, FOSDEM) plus a lunch with the two founders on 16 Sep 2026. Anything that comes only from that lunch is marked [lunch] and should be read as their account, not established fact. People first, then technical, then roadmap, then why I think it matters to the two of you.
1. Timeline
| When | What happened | The people |
|---|---|---|
| 2014 | Esperanto Technologies founded in Mountain View by Dave Ditzel (Transmeta co-founder, ex-Sun/Intel). Thesis: a thousand tiny in-order RISC-V cores at near-threshold voltage beat a GPU on inference energy. | Ditzel CEO; Jayesh Iyer (ex-Intel Labs) Fellow and Chief Architect; Roger Espasa, Allen Baum, Grigorios Magklis, Jose Renau, Tom Riordan, Tommy Thorn on the architecture. Offices later in Austin, Portland, Barcelona, Belgrade. |
| Nov 2018 | $58 M Series B, $63 M cumulative; Almaz Capital and Western Digital in. NetSpeed Systems licensed as the NoC vendor (May 2018); Intel bought NetSpeed four months later. | Almaz's deal team: Alexander Galitsky and Geoffrey Baehr. Tanya Dadasheva was an Almaz analyst then; Esperanto was in her portfolio. |
| Mar 2019 | Facebook's OCP programme: an M.2 inference module spec on the Glacier Point v2 carrier, six dual-M.2 cards per carrier, twelve accelerators per Yosemite v2 sled, all air-cooled. Facebook named Esperanto, Habana, Intel, Marvell and Qualcomm as vendors. Esperanto sized its die to fit. | Facebook later built its own chip (MTIA, from 2020) for the same recommendation workloads. |
| Late 2019 / 2020 | The 2019 tape-out target slipped. Art Swift (ex-MIPS, Wave) replaced Ditzel as CEO. A further $61 M reported in Apr 2021 (~$124 M lifetime). | Ditzel stayed as founder and chief technologist. |
| 24 Aug 2021 | Hot Chips 33: ET-SoC-1 disclosed. TSMC 7 nm, 570 mm², 24 B transistors, 1,088 ET-Minion cores (RV64IMFC + 8-lane vector/tensor unit, 2 harts each) in 34 shires, 4 ET-Maxion out-of-order cores, >160 MB on-die SRAM, 8 LPDDR4x channels, PCIe Gen4 x8, ~20 W per chip. | Ditzel presented; Iyer was the architect. |
| 2021–2024 | Silicon shipped at 600 MHz instead of the >1 GHz design point. Ditzel's 2026 slide: a timing bug from a full-custom register file, "CAD tool problem, workaround was just to raise voltage a bit." The recsys market moved to transformers and to in-house hyperscaler silicon. | Tanya hosted Ditzel on Almaz's podcast (Oct 2021) and fundraised for Esperanto in 2020 (Toyota to G42). |
| 2022 | After the invasion of Ukraine, Tanya left Almaz (between Aug and Oct 2022). She and Roman Shaposhnik (Sun compiler engineer 2001–09, Cloudera, Pivotal, founder of Apache Bigtop, founding CTO of ZEDEDA, ASF VP Legal Affairs 2018–Jul 2026, FFmpeg maintainer for DV and Sparc) set up a Cyprus company together. | The two have co-hosted every AI Plumbers event since. |
| 2023 | Ainekko, Co. incorporated in Delaware. First plan: an open software stack for edge inference, "something like Mojo" [lunch]; the question was which hardware to build on. They tried Tenstorrent (community partner, Wormhole cards at their events) and Esperanto boards. | Tanya CEO, Roman Head of Software / CTO. First public appearance at AI.dev, SF, Dec 2023. |
| Jul 2024 | AI Hack Lab in Cyprus; the AI Foundry community exists before any chip. | |
| Feb 2025 | First AI Plumbers / low-level AI engineering devroom at FOSDEM (60+ proposals, 26 talks). Editions followed in Ghent, Berlin, San Francisco (Studio 45, Oct 2025) and Brussels (Feb 2026, ~3,000 in the room). | Co-organisers: Jarek Potiuk, William Jones, Matt Topol, plus Hugging Face's Vaibhav Srivastav. |
| Jul 2025 | Esperanto winds down its silicon business. Peak headcount 140; Mountain View cut 90%; Spain and Serbia closed. Swift blamed "incredible raids by deep-pocketed competitors." Ainekko had been running on Esperanto silicon for about six months and first tried to partner, then to buy. | [lunch] A group of roughly 35 engineers led by Jayesh Iyer left en masse for Tesla before the wind-down, joined Dojo, and were redirected to the AI5/AI6 inference chip when Dojo was shut in Aug 2025. Others went to Barcelona's SemiDynamics (CEO Roger Espasa, ex-Esperanto) and OpenChip. |
| 15 Sep 2025 | First Form D: $2.15 M from one investor. Company moves into Studio 45, a makerspace in Bernal Heights, SF. | Angel: Alexander Galitsky. Board: Wensi Wu (WI Harper). |
| 22 Oct 2025 | AI Foundry platform launched at the RISC-V Summit, Santa Clara: "open-source principles and do-ocracy for AI hardware." | Jayesh Iyer gives a supporting quote in the release. |
| 19 Nov 2025 | Ainekko acquires Esperanto's IP and selected assets (price undisclosed; a private asset purchase, not a bankruptcy sale). Roman at the summit: RTL "in a month or two", the NoC "later next year." | Eight ex-Esperanto engineers joined at peak [lunch]. |
| 29 Jan 2026 | Merger with Veevx (Chandler, Arizona + India): MRAM-based iRAM memory plus a team that has done end-to-end tape-outs. Combined company keeps the Ainekko name. | Douglas Smith (Motorola SPS, then 25+ years leading Broadcom design teams, 200+ tape-outs; self-funded Veevx) becomes third cofounder, Head of Silicon, and a director. Leo Spiegel (Veevx COO) becomes an advisor. Form D of 20 Feb 2026: $24.9 M offering, $14.7 M sold, business-combination flag set (stock, by inference). |
| Mar–Jun 2026 | CORE-ET accepted as an OpenHW Foundation / Eclipse project (creation review 4 Mar; public RTL 4 May; announced 2 Jun). Hardware licence Solderpad 2.1 (repos stamped Apache-2.0), software Apache 2.0. | Project leads: Roman and Milind Bhandarkar. Committers include Gianluca Guida (VP Software, ex-Xen/MINIX), Martin Chang, Felix LeClair (ex-Tenstorrent), Eric Hallahan. |
| Apr 2026 | Erbium taped out: one neighbourhood of 8 Minions with 16 MB of Veevx MRAM as L2 plus OTP, on a TSMC 16 nm shuttle, nine months after the IP landed. Fourteen ET-SoC-1 errata fixed on the way. | Douglas Smith's team did the physical design. |
| May 2026 | Tanya's manifesto "The Next Thousand Chips": "If you can reliably vibe-code RTL, you don't need the layers above it." | |
| Jun 2026 | Tanya keynotes RISC-V Summit Europe (Bologna): "we absolutely do not plan to tape out the same chip again"; letting agents mutate the RTL gave "improvements to 100×" in internal runs. | Afonso Oliveira and Felix LeClair present core-et and et-simd. |
| 1–27 Jul 2026 | CORE-ET hackathon on real ET-SoC-1 boards with Hugging Face: 224 PRs reviewed. Llama 3.2 1B at 17.9 tok/s; YOLOv10n ~90× faster than the naive FP32 port; ET backend upstreamed into llama.cpp (Jul 10). | Afonso Oliveira (boards, reviews), Eric Hallahan (compiler), Martin Chang (llama.cpp), Saqib Akram and Saad Bin Nasir (10xEngineers, KernelX), Rehan Qasim, Rui Moura, Rich Neale (independent Rust driver et-rs). |
| 25 Aug 2026 | Cool Chips – Hot Takes, Palo Alto: Ditzel's Esperanto retrospective and AMA; Roman on hyper-specialisation; Allen Rush (Chief Architect, ex-AMD Senior Fellow) on AI-assisted semiconductor engineering. | Talks published 4 Sep. |
| 2 Sep 2026 | Nvidia signs to acquire Hugging Face (~$12.9 B, close expected H1 2027). Ainekko's HF collaboration (contract into early 2027 [lunch]) now sits inside a competitor. | |
| Sep 2026 | Roman ports an MPEG-2 decoder from FFmpeg to bare-metal ET-SoC-1 with his agent harness (2.6–3.4× over the scalar ET baseline, CPU still faster, "no power-efficiency claim"). Erbium silicon due back from TSMC [lunch]. Headcount about 20 across the Valley, Arizona, Europe and India [lunch] (EE Times said ~35 at the merger). | Roman at the U.S.–Romania AI & Business Summit, Timișoara, 22–25 Sep. |
2. Who went where
The Esperanto diaspora. Ditzel gives retrospectives and says the open RTL is unaffected by the silicon bug. Jayesh Iyer went Esperanto → Tesla (Dojo, then AI5/AI6) → Apical Intelligence, the renamed Numenta (Menlo Park; CEO Dan Steere, Chief Scientist Subutai Ahmad), where he is Chief Architect. Roger Espasa runs SemiDynamics in Barcelona, which had built RISC-V cores for Esperanto as a client. A handful joined Ainekko; most of the 140 scattered across the Valley, Barcelona and Belgrade. Peter Cawley (corsix) documents the chip independently and gave the FOSDEM talk on programming it.
Ainekko's own lineage is three strands that did not start together. Software and open source: Roman (Sun, Apache, ZEDEDA), Gianluca Guida (Xen, HURD, MINIX; Cambridge UK), Milind Bhandarkar (Hadoop). Venture and operations: Tanya and Dan Stolyarov (COO), both ex-Almaz Capital. Silicon: Douglas Smith and the Veevx team (Arizona and India, Broadcom-trained, memory-first), and Allen Rush from AMD. The company's own line is that the chips are not the goal: revenue is design-partner work, tools and IP blocks, with a tape-out every nine months.
The community, which is where the work happens. A Discord of contributors and a lab at Studio 45 where community members get SSH access to ET-SoC-1 cards: an independent Rust driver (et-rs), an LLVM fork with the ET extension merged upstream as XAIFET (Jan 2026), a functional simulator (sw-sysemu), llama.cpp and ONNX ports, a New York trader running strategies on a community card [lunch], and Ry Bruscoe (Anomly), who has implemented a bounded-posit datatype as SystemVerilog targeting the Minion vector/tensor unit (open-bposit); Roman says it was agent-written and is being pitched to Nvidia [lunch]. Hugging Face, Ultralytics and Liquid AI are listed as model builders co-optimising for the silicon. Tenstorrent sponsors the AI Plumbers events with hardware; a couple of ex-Tenstorrent people have joined.
3. What they are doing now
3.1 The substrate, and what "open" actually contains
CORE-ET is the Minion core, the 8-core neighbourhood, a re-translated shire cache and RBOX, the page-table walker, and the ET-Link protocol definition, with Verilator simulation, cycle-by-cycle co-simulation against the original RTL, and Yosys synthesis to iCE40/Xilinx/ECP5. Not open: the mesh NoC (NetSpeed, now Intel's IP), the PCIe and DDR controllers (Synopsys DesignWare), the Maxion cores, and Veevx's MRAM macros (proprietary). Erbium's small interconnect is Arm NI-700 with an open crossbar stub for simulation. So a full 1,088-core re-spin is not on the table, and the founders say so. What is on the table is any topology of 8-core tiles you can wire yourself.
The chip is unusual in three ways that matter for energy work: every core is in-order and single-issue, so cycle counts are exact and predictable; the L1 and shire caches are software-managed scratchpads with no hardware coherence (Tanya: "a footgun with a hair trigger"); and the per-shire voltage rails and the 6 W-for-a-thousand- cores floor (Ditzel's measured DLRM numbers: 1,000 Minions at 600 MHz, 6 W; 128 MB SRAM, 2.8 W; NoC, 1.8 W; whole card 13.5–22 W) put the algorithmic signal above the idle floor in a way a 400 W GPU never does. Precision on Minion1: FP32, FP16 with FP32 accumulate, INT8 to INT32; no BF16, no FP8.
3.2 Memory first: iRAM
Veevx's MRAM-based iRAM claims 3 ns reads, >10¹² endurance, non-volatility, and denser-than-SRAM footprints (Roman told EE Times it saves about a quarter of the die area vs SRAM; at lunch he called the density not SRAM-level, so ask). Erbium uses 16 MB of it as L2. The stated direction is a gigabyte-class non-volatile weight store on the same die or package, aimed at models under ~1 B parameters, with standby power near zero. Douglas Smith's group is also prototyping, on TSMC 5 nm, a way to extract roughly 50% more usable bits from a memory cell by exploiting the analog distribution of the cell, first without added noise, with noisy-weight memory as an explicit follow-on [lunch]. They have talked with Konstantin Novoselov's group (NUS Institute for Functional Intelligent Materials, in-materia and memristive computing) about materials that could give MRAM tunable distributions [lunch].
3.3 Agents that edit the RTL
The distinctive claim is procedural. With the chip fixed, their internal and public hackathons hit a ceiling; once agents are allowed to change the RTL as well as the kernel, they report some models running ~100× faster in simulation, with the physical-design loop still closed by humans ("goes through the human head for now"). The published evidence is Allen Rush's July 2026 white paper: selected functional and routed-block results for an agent-generated YOLO accelerator, an 11,154 fps figure that is a 1 GHz design-point calculation, and an explicit statement that full-core closure, GDS and silicon were not achieved. Their own multi-agent system now does full PCB layouts [lunch]. Roman runs Anthropic models through Shelley, exe.dev's open-source harness, rather than a vendor harness, and marks PRs as AI-authored or human-authored.
3.4 Software
GCC is canonical; the LLVM fork has an active dev branch; tensor ops are CSR writes so stock Rust and LLVM work.
Runtime, firmware, driver, emulator and manuals are public. Boards: no store and no price; a community lab slot is
requested on Discord; GWDG Göttingen runs a public ET-SoC-1 system. Best published inference: Llama 3.2 1B at
~17.9 tok/s on 14–16 W. KernelX (10xEngineers) took Qwen 3.5 35B-A3B decode from 2.4 to 19 tok/s in six days on
the same board; on a Groot VLA the chip was slower than an AGX Orin (1,130 vs 429 ms).
3.5 Business
Physical AI at the edge: drones, robots, vehicles, factory floors. Tanya, Nov 2025: "we don't want to go for the data center." Customers described as autonomy and drone companies, some military, who value open RTL because it protects them from vendor death. Revenue model: design partners, tools, IP blocks, a tape-out every nine months. Investors on record: WI Harper, Silicon Catalyst, Galitsky as angel; Constructor Capital lists them.
4. Roadmap, as stated
| Item | Public record | Said over lunch, 16 Sep 2026 |
|---|---|---|
| Erbium (8 Minions + 16 MB MRAM, 16 nm) | Taped out Apr 2026 on a TSMC shuttle | Silicon back from TSMC imminently; first prototypes route the NoC through an FPGA |
| Next part | Site: composable 8 to 4,000+ cores; deck mentions a 256-core class part | A 64-core part for drones and physical AI is the target for current customers; chiplet-based; packaging, not die size, sets thermals |
| Network on chip | NetSpeed in ET-SoC-1 silicon; Esperanto's own NoC for the next generation promised "later next year" (Oct 2025), unreleased | They own Esperanto's second, in-house NoC design and will use it; ask to see it |
| Process | "staying at 16 and we're fine with that" (Roman, Aug 2026) | 16 nm capacity is easy; 5 nm is not obtainable for a startup |
| Prototyping | FPGA flow to iCE40/Xilinx/ECP5 for one neighbourhood | A universal prototype board where any topology or dataflow can be tried side by side against the fixed cores, with the winners taped out for customers |
| Datatypes | FP32/FP16/INT8 on Minion1; Minion2 (FP8, RVV) designed but not open | Community posits; customers using BitNet-style ternary |
| Video | FFmpeg fork with MPEG-2 offload (Sep 2026) | The whole FFmpeg on the 32 GB card, decoder feeding the model directly |
| Partners | Hugging Face, Ultralytics, Liquid AI | HF contract into early 2027 despite the Nvidia acquisition; joint hackathon floated |
| Events | AI Plumbers devroom, FOSDEM 30–31 Jan 2027 | A talk at the Monday group in San Francisco around 28 Sep 2026 |
5. Why this should interest the two of you
Thomas. spicenn2 asks whether transistors and capacitors can learn MNIST at microjoules per image, scored on accuracy and energy together. Ainekko is the digital control group for that question: a substrate where every byte moved and every cycle spent is knowable, with per-shire rails you can lower, on which the same accuracy-vs- joules frontier can be measured rather than simulated. Three specific overlaps: (1) Douglas Smith's bit-extraction work is the same bet as Normal's, that the analog distribution of a cell is information rather than noise, made by a memory designer rather than a physicist; (2) their MRAM roadmap wants a noisy-weight tier, which is your CN101 argument arriving from the other side; (3) nobody has computed a gradient on this chip. A learning kernel on Erbium-class hardware, scored in measured joules, would be the first non-NVIDIA training number in the open, and they have said they would host that work on community cards.
Mitchell. Sphere Semi automates analog and RF design with agents; Ainekko is the digital mirror image, a team claiming that agents editing RTL against a transparent substrate beat any closed NPU. Their evidence is a white paper that stops short of closure, and their physical-design loop is still human, which is exactly the gap Sphere lives in. Two more overlaps: Luminous's lesson that interconnect, not compute, is where the money and the risk sit is their lesson too (their NoC is the one block they could not open, and the one they say they now own); and Veevx's memory- first thesis is the RRAM analysis you did at Luminous, redone with MRAM by people who can tape out. They are also short of exactly the person you described as rare: someone who knows the analog noise distributions well enough to close digital on top of them. Douglas Smith is that person on their side; the meeting is with him, not the founders.
For both: the founders are hosting a hackathon-style engagement with Hugging Face, are open to outside experiments on their boards, and will be in San Francisco from late September. The lab is inside Studio 45 at 45 29th Street.
6. Sources
Ditzel, Hot Chips 33 slides (Aug 2021) and Esperanto retrospective (Cool Chips – Hot Takes, 25 Aug 2026, published blog.aifoundry.org) · Facebook OCP post, 14 Mar 2019 · EE Times: Esperanto wind-down (Jul 2025), Ainekko buys Esperanto IP (19 Nov 2025), Veevx merger (30 Jan 2026), Jim Keller on Tenstorrent (Jul 2026) · GlobeNewswire releases 22 Oct 2025, 19 Nov 2025, 29 Jan 2026 · SEC Form Ds filed 29 Sep 2025 and 20 Feb 2026 · nekko.ai, et-core.nekko.ai, veevx.com · openhwgroup/core-et, aifoundry-org/erbium, et-platform, et-rs, open-bposit · Allen Rush, AI-Assisted Semiconductor Engineering white paper (Jul 2026) · Tanya Dadasheva, "The Next Thousand Chips" (May 2026) and hackathon retrospective (Jul 2026) · FOSDEM 2025/2026 speaker pages and AI Plumbers CfP · Apical Intelligence team page · TechCrunch on Dojo (7 Aug 2025), Cerebras and Nvidia–Hugging Face (2026) · corsix.org, "Esperanto lives on" (Oct 2025) · Lunch with Roman Shaposhnik and Tanya Dadasheva, San Francisco, 16 Sep 2026.